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BD7844AEFV
Datasheet
● Function explaining - continued
2-1. PWM0 to PWM15 register data
The brightness of output terminal OUT0 to OUT15 is set by the register data of PWM0(address:00h) to
PWM15(address:0Fh).
The PWM brightness control in 256 steps is possible from 00h (complete off) to FFh (complete on). Brightness can
formulate by followings (PWM n [7:0] means each register value of PWM0-PWM15).
ILED = ILEDmax x PWM n [7:0] / 256
ILED = ILEDmax
(PWM n [7:0] = 00h-FEh)
(PWM n [7:0] = FFh)
2-2. Mode1 registers data
The operation mode of BD7844AEFV is set according to mode1 register (address: 1Ah) data.
Table 4 shows the allocation of the bit of mode1 register data.
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Bit name
LIMITRESET
PROTECT0
Reservation
PWMSLOW
Reservation
Reservation
PROTECT1
ALLCALL
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
*
1
0
*
1
*
1
*
1
0 *
1
1
0
1 *
Function
Device limitation software reset : off
Device limitation software reset : on
Please write “0”.
It is not recognized as Mode1 register data at “1”.
Please write “0”
Prohibited
PWM period is 60kHz
PWM period is 2kHz
Please write “0”.
Prohibited
Please write “0”.
Prohibited
Please write “1”.
It is not recognized as Mode1 register data at “0”.
It doesn't respond to the slave address for all call.
It responds to the slave address for all call.
The START condition is sent by the I C bus master.
*Default value after reset
Table4. Mode1 register (Address: 1Ah) data
Mode1 register data cannot be set by the auto increment option. Please set it alone by the following format. In the
correct execution, there should not be device that monopolizes the bus.
2-3. Mode1 register data setting procedure
2
1. The slave address of BD7844AEFV that wants to be set by mode1 register is sent by the master.
2. When the slave address is sent and recognized, the master sends mode1 register address [00011010] (1Ah).
It is recognized only when LSB 5bit are [11010] and the auto increment option in MSB 3bit are [000].
3. When mode1 register address is sent and recognized, the master sends mode1 register data.
It recognizes it as data only when the data confirmation bit (bit 6=0 and bit1=1) is all correct.
4. When correct mode1 register data is sent and recognized, the master sends the STOP condition to end mode1
setting command. Afterwards, LIMITRESET, PWMSLOW, and ALLCALL become effective.
3.
Reset
BD7844AEFV has four kinds of resets (power on, software, device limitation software, external,).
3-1. Power-on reset
When the power supply is forced to VDD, internal power-on reset maintains BD7844AEFV in the state of reset until
VDD reaches Vpor. Reset is liberated at Vpor, and the register and the I 2 C bus state machine of BD7844AEFV are
initialized in the state of default.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
10/14
TSZ02201-0G3G0CZ00310-1-2
15.Oct.2012 Rev.001
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